1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device, and more particularly, it relates to a semiconductor device comprising a semiconductor chip including a circuit and a method of fabricating a semiconductor device.
2. Description of the Background Art
A semiconductor device comprising a semiconductor chip including a circuit is known in general, as disclosed in Japanese National Patent Publication Gazette No. 2002-512436, for example.
The aforementioned Japanese National Patent Publication Gazette No. 2002-512436 discloses a structure of a semiconductor device comprising a semiconductor chip (die) including a circuit, an extension pad (metallic pad) connected to a circuit part of the surface of the semiconductor chip and a wire (metallic contact) connected to a conductive terminal (solderable bump) set under the semiconductor chip while connecting the wire to a side end surface of the extension pad exposed by machining.
In the structure of the semiconductor device disclosed in the aforementioned Japanese National Patent Publication Gazette No. 2002-512436, however, the surface of the side end of the extension pad exposed by machining is disadvantageously roughened. Further, chips resulting from the machining disadvantageously adhere to the side end of the extension pad. When the surface of the side end of the extension pad is roughened or chips adhere to this side end, it is disadvantageously difficult to excellently connect the wire to the side end of the extension pad.
In order to solve the problem of the semiconductor device disclosed in the aforementioned National Patent Publication Gazette No. 2002-512436, therefore, a structure of a semiconductor device obtained by removing an insulator film covering the lower surface of an extension pad by etching thereby exposing the lower surface of the extension pad while connecting a wire to the lower surface of the extension pad is proposed in general.
FIG. 36 is a side elevational view showing the overall structure of the aforementioned conventional proposed semiconductor device 150. FIG. 37 is a sectional view showing a structure in the vicinity of an end of the conventional proposed semiconductor device 150. In the conventional proposed semiconductor device 150, a glass substrate 103 is mounted on a semiconductor element 101 through a resin layer 102, as shown in FIG. 36. A plurality of semispherical conductive terminals 104 are provided on the lower surface of the semiconductor element 101. The semiconductor element 101 comprises a semiconductor chip 105, as shown in FIG. 36. This semiconductor chip 105 has a structure obtained by forming a circuit (not shown) on a silicon substrate. An insulator film 106 of SiO2 is formed on the upper surface of the semiconductor chip 105. A plug electrode 107 is formed to be embedded in the insulator film 106. This plug electrode 107 is connected to the circuit (not shown) formed on the upper surface of the semiconductor chip 105.
An insulator film 110 of SiN is formed to cover the upper surface of the insulator film 106. A contact hole 112 is formed in a region of the insulator film 110 corresponding to the plug electrode 107. An extension pad 113 is formed on a prescribed region of the insulator film 110. A wire 114 is formed at a prescribed interval from the extension pad 113. This wire 114 is connected to the plug electrode 107 through the contact hole 112 of the insulator film 110. An insulator film 115 is formed to cover the overall surface. The insulator film 115 has an irregular upper surface reflecting the shapes of the extension pad 113 and the wire 114 formed at the prescribed interval. The resin layer 102 (see FIG. 36) is formed to fill up the irregular upper surface of the insulator film 115, and bonds the glass substrate 103 as an adhesive.
An insulator film 117 is formed to cover the side surface and the lower surface of the semiconductor chip 105 and a prescribed region of the lower surface of the insulator film 106. A buffer member 118 is provided on a prescribed region of the lower surface of the insulator film 117 corresponding to the lower surface of the semiconductor chip 105. A wire 116 is formed on the insulator film 117 and the buffer member 118 to extend along the side surface and the lower surface of the semiconductor chip 105. This wire 116 is connected to the lower surface of the extension pad 113 exposed by partially etching the insulator films 106 and 110. Each of the aforementioned semispherical conductive terminals 104 is provided on the lower surface of a region of the wire 116 corresponding to the buffer member 118. Thus, the extension pad 113 and the conductive terminal 104 are connected with each other through the wire 116. A further insulator film 108 is formed to cover a prescribed region of the wire 116 while a protective film 109 is formed to cover the insulator film 108.
FIGS. 38 to 54 are sectional views for illustrating a fabrication process for the conventional proposed semiconductor device 150 shown in FIG. 37. The fabrication process for the conventional proposed semiconductor device 150 shown in FIG. 37 is now described with reference to FIGS. 37 to 54.
As shown in FIG. 38, a semiconductor wafer 105a formed with circuits (not shown) on the upper surface thereof is prepared. The insulator film 106 of SiO2 is formed on the semiconductor wafer 105a while plug electrodes 107 to be connected to the circuits (not shown) of the semiconductor wafer 105a are formed to be embedded in the insulator film 106. The insulator film 110 of SiN is formed to cover the insulator film 106 and the upper surfaces of the plug electrodes 107.
As shown in FIG. 39, contact holes 112 are formed in the regions of the insulator film 110 corresponding to the plug electrodes 107 by photolithography and etching.
As shown in FIG. 40, a metal layer 113a is formed to fill up the contact holes 112 of the insulator film 110 while covering the upper surface of the insulator film 110.
As shown in FIG. 41, the metal layer 113a is patterned by photolithography and etching thereby forming a plurality of extension pads 113 and a plurality of wires 114 at prescribed intervals.
As shown in FIG. 42, the insulator film 115 is formed to cover the overall surface.
As shown in FIG. 43, the resin layer 102 is formed to cover the upper surface of the insulator film 115 while bonding the glass substrate 103 as the adhesive.
Thereafter wet etching is performed from the lower surface of the semiconductor wafer 105a thereby separating the semiconductor wafer 105a into a plurality of semiconductor chips 105 as shown in FIG. 44.
As shown in FIG. 45, the insulator film 117 is formed to cover the lower surfaces and the side surfaces of the semiconductor chips 105 and the lower surface of the region of the insulator film 106 located between the adjacent pair of semiconductor chips 105.
As shown in FIG. 46, resist films 119 are formed to cover regions of the insulator film 117 corresponding to the side surfaces and the lower surfaces of the semiconductor chips 105 and partial regions located under the extension pads 113. The resist films 119 are employed as masks for performing wet etching from under the insulator film 106 with hydrofluoric acid thereby partially removing the insulator films 117 and 106 of SiO2. Thus, the lower surface of a prescribed region of the insulator film 110 consisting of SiN is exposed as shown in FIG. 47. Further, wet etching is performed from the side of the exposed lower surface of the prescribed region of the insulator film 110 with hot phosphoric acid thereby removing the prescribed region of the insulator film 110 consisting of SiN. Thus, partial regions of the lower surfaces of the extension pads 113 and the region of the lower surface of the insulator film 115 located between the adjacent pair of extension pads 113 are exposed as shown in FIG. 48.
As shown in FIG. 49, buffer members 118 are formed on the regions of the insulator film 117 corresponding to the lower surfaces of the semiconductor chips 105.
As shown in FIG. 50, a metal layer 116a is formed to cover the exposed partial regions of the lower surfaces of the extension pads 113, the region of the lower surface of the insulator film 115 located between the adjacent pair of extension pads 113, the buffer members 118 and the insulator film 117.
As shown in FIG. 51, a region of the metal layer 116a located under the space between the adjacent pair of extension pads 113 is removed by photolithography and etching. Thus, the metal layer 116a is divided for the respective semiconductor chips 105, thereby forming two wires 116 connected to the lower surfaces of the extension pads 113 respectively.
As shown in FIG. 52, insulator films 108 are formed to cover prescribed regions of the wires 116 and prescribed regions of the lower surface of the insulator film 115. Thereafter the protective film 109 is formed to cover the insulator films 108 and the region of the lower surface of the insulator film 115 located between the adjacent pair of extension pads 113.
As shown in FIG. 53, the semispherical conductive terminals 104 are formed on the lower surfaces of regions of the wires 116 corresponding to the buffer members 118.
As shown in FIG. 54, dicing is performed from the lower side along the center line of the region located between the adjacent pair of semiconductor chips 105. Thus, the conventional proposed semiconductor device 150 is formed as shown in FIG. 37.
In the conventional proposed semiconductor device 150 shown in FIG. 37, however, the extension pad 113 for electrically connecting the semiconductor chip 105 and the external wire 116 with each other is formed to be in contact with the upper surface of the insulator film 110 of SiN formed on the insulator film 106 of SiO2, and hence the insulator film 106 of SiO2 and the insulator film 110 of SiN must disadvantageously be individually wet-etched with different etching solutions (hydrofluoric acid and hot phosphoric acid) respectively when the lower surface of the extension pad 113 is exposed for connecting the wire 116. Thus, the step for exposing the lower surface of the extension pad 113 is so complicated that the fabrication process for the semiconductor device 150 is also complicated.